This invention relates to the field of electronic circuits, and, more particularly, to a programmable logic device including a bi-directional shift register.
Conventional field-programmable gate arrays (FPGAs) use re-programmable lookup tables for implementing functions having n inputs, where n depends on the lookup table size and the addressing scheme involved. Such a lookup table can normally implement 2{circumflex over ( )}2{circumflex over ( )}n logic functions. A logic function may or may not use all the inputs to the lookup table. A few of the logic functions that may be accommodated in the lookup table include AND, NAND, OR, NOR, XOR, XNOR and mixed combinations of these functions. It may also be desirable to implement a shift register functionality within the logic element (lookup table) to maximize the flexibility of the lookup table.
U.S. Pat. No. 5,889,413 to Bauer discloses one prior art approach for using lookup tables as shift registers. The key elements that enable shift operation are a pass transistor/CMOS transmission gate and an inverter which connect the latches in the lookup table structure. Although such an arrangement enables shift operation within the lookup table, it does so only in one direction. It does not have any provision for shifting the data bits in both directions. This limits its usage to applications involving unidirectional shift operations. Thus, this approach fails to accommodate applications involving bi-directional shift operations.
An object of the invention is to provide a programmable logic device including a bi-directional shift register.
This and other objects, features, and advantages in accordance with the present invention are provided by a programmable logic device which may include a programmable interconnect structure and a plurality of configurable logic elements including data latches interconnected by the interconnect structure. At least one of the configurable logic elements may be configurable as both a shift register and as a lookup table. Furthermore, the shift register may operate as a bi-directional shift register by the inclusion of first means or circuitry for configuring the data latches either as series connected inverters during shift operations or as data latches after each shift operation. In addition, second means or circuitry for selecting a direction of shifting may also be included, as well as third means or circuitry for supplying data to the input of the shift register as determined by the direction of shifting.
More particularly, the first means may include first and second sets of switches (or transmission gates) connected between the inverters of each latch and between each latch and each subsequent latch in the selected direction of shifting in the shift register chain, respectively. Their arrangement may be such that the first set of switches connect the inverters as latches during normal operation, while during a shift operation the second set of switches connect one inverter of each latch to an inverter of the subsequent latch for transferring data. The second and third means may include logic gates, e.g., metal oxide semiconductor (MOS) gates.
The above programmable logic device may further include control logic for controlling shifting when the configurable logic element is configured as a bi-directional shift register. The control logic may include a user clock terminal for controlling shifting of data between the plurality of data latches. Further, second control logic may also be included for controlling the manner in which the logic elements are configured as a bi-directional shift register.
The second control logic may include a first coupling means or device for coupling a data input terminal to either the first data latch or to the last data latch depending on the selected direction of shifting. In addition, a second coupling means or device may be included for coupling a data output terminal to the output of any of said data latches.
The second coupling means may include selection means or circuitry for selecting one or more of the outputs of the data latches as the final output, and the selection means may include one or more decoders. Also, multiple programmable logic devices may be interconnected to implement a bi-directional shift register of a length greater than the size of a single programmable device.